An Enhanced Debug-Aware Network Interface for Network-on-Chip

M. H. Neishaburi and Zeljko Zilic
McGill University


As new SoCs tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are becoming so complex. Such an increase in complexity of cores and on-chip communication has accentuated the need to review and enhance traditional debug methods for System on Chips (SoCs). In this paper, we consider NoC as a functional interconnection among cores and propose debug aware network interface (NI). The proposed interface provides a mechanism for cross-trigger debugging. Transactions issued by a processing element connected to the proposed debug aware NI are monitored by the proposed cross-trigger unit and trace data and trigger events will be extracted and routed to another processing element or Shared Debugging Unit (SDU). SDU combines debug traces from different processing elements. The major benefits of using our proposed architectures for debugging over traditional techniques are as follows: 1) the proposed debug aware NI can detect, mark and bypass severe faulty conditions such as deadlocks resulting from design errors or electrical faults in real time 2) there is no need for a large internal trace memory inside processing element because SDU can communicate to the external memory.