Fast Reliability Exploration for Embedded Processors via High-level Fault Injection

Zheng Wang,  Chao Chen,  Anupam Chattopadhyay
MPSoC Architectures, RWTH-Aachen


The downscaling of technology features have brought the system developers an important design criteria, reliability, into prime consideration. Due to external radiation effects and temperature gradients, the CMOS device is not anymore guaranteed to function flawlessly. Admission for errors to occur is also helpful as that increases the power budget. The power-reliability trade-off compounds the system design challenge by adding another metric, for which efficient design exploration framework is needed. In this work, we present a high-level design framework extended with the capability of fault injection, an important ingredient of reliability-driven design. Compared to traditional HDL-based fault injection, the proposed fault injection during instruction-set simulation is significantly faster without any notable loss of accuracy. The fault injection framework also allows quick exploration of fault prevention measure both by the aid of software and hardware techniques. We demonstrate the effectiveness of our approach by one case study with a RISC processor customized for cryptographic application, where fault protection plays a major role. We also benchmark our framework with a state-of-the-art HDL-based fault injection framework.