A System-level Solution for Managing Spatial Temperature Gradients in Thinned 3D ICs

Arunachalam Annamalai,  Raghavan Kumar,  Arunkumar Vijayakumar,  Sandip Kundu
University of Massachusetts Amherst


As conventional CMOS technology is approaching scaling limits, the shift in trend towards stacked 3D Integrated Circuits (3D IC) is gaining more importance. 3D ICs offer reduced power dissipation, higher integration density, heterogeneous stacking and reduced interconnect delays due to reduced wire lengths. In a 3D stack, all but the bottom tier are thinned down to enable through silicon vias (TSV). However, the thinning of the substrate increases the lateral thermal resistance resulting in higher intra-layer temperature gradients potentially leading to performance degradation and even functional errors. In this work, we study the effect of thinning the substrate on temperature profile of various tiers in 3D ICs. Our simulation results show that the intra-layer temperature gradient can be as high as 57 C. The conventional static solutions of performance guard-banding or stringent design margining to mitigate such large gradients lead to highly inefficient design. To this end, we present a system-level situation-aware integrated scheme that performs opportunistic thread migration and dynamic voltage and frequency scaling (DVFS) to effectively manage thermal violations while increasing the system throughput relative to stand-alone schemes.