Improving Timing Error Tolerance without Impact on Chip Area and Power Consumption

Ken Yano,  Takanori Hayashida,  Toshinori Sato
Fukuoka University


The demand of power saving and highly dependable LSI has increased by the miniaturization of device process technology and the spread of portable devices such as mobile phones. The design method which takes the worst case scenario makes the design margin too large because of the parameter variation in the deep submicron domain and it has bad influence for performance and power consumption. To decrease design margins, typical-case design method with canary FF has been proposed so far. We explain how canary FF can be integrated in usual digital LSI design flow in detail and analyze the area and power overhead compared with the worst-case design method. Canary FF can detect timing error caused by environmental or manufacturing variations, aging deterioration and by transient error known as soft error in deep submicron domain. Proposed implementation method selectively replaces normal flip-flops with canary flip-flops in order to decrease area and power overhead. The overheads of selective canary FF replacement are investigated by implementing conventional processor cores; miniMIPS and MeP (Media Embedded Processor). The results show that our method can save chip areas effectively and power overhead can be reduced to very small. By adopting selective canary FF replacement method, it is possible to design LSI by focusing on typical case but not on worst case analysis.