Peak Power Reduction of a Sensor Network Processor Fabricated With Deeply Depleted Channel Transistors in 65nm Technology

Kentaro Kawakami,  Takeshi Shiro,  Hironobu Yamasaki,  Katsuhiro Yoda,  Hiroaki Fujimoto,  Kenichi Kawasaki,  Yasuhiro Watanabe
Fujitsu Laboratories Ltd.


We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. Measurement result shows that the reduced Vth variation of the DDC process improves 44 % and 15 % of operating frequency or 150 mV and 50 mV of supply voltage margin for the MCU and the SRAM, respectively. Thanks to the improved supply voltage margin, the DDC operates at lower supply voltage and achieved 20.1 % and 19.0 % of power reduction for the MCU and 320 KB SRAM, respectively. The paper has also discussed the optimal voltage control method, which is suitable for the various applications of sensor network processors.