Minimizing Simultaneous Switching Noise at Reduced Power with Constant-Voltage Power Transmission Lines for High-Speed Signaling

Satyanarayana Telikepalli,  Madhavan Swaminathan,  David Keezer
Dept. of Electrical & Computer Engineering, Georgia Institute of Technology


Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme called Constant Voltage Power Transmission Line (CV-PTL) is shown to significantly reduce switching noise while also lowering power consumption. This concept has been demonstrated through theory, simulation, and measurements.