Performance Entitlement by Exploiting Transistor’s BTI Recovery

Senthil Arasu1,  Mehrdad Nourani1,  Vijay Reddy2,  John Carulli3
1Univ. of Texas at Dallas, 2Texas Instruments Inc, Dallas, 3Texas Instruments Inc. Dallas


The inherent problem in signal probability prediction has limited the scope of exploiting the transistor’s BTI recovery at circuit level. In this paper, we present a design-for-reliability (DFR) methodology for digital designs, BTI_Refresh, that instead of relying on predicting signal probability, sets (controls) it to a known value (~0.5) such that the BTI stress effects are alleviated and a predicted recovery effects could be guaranteed at circuit level. The technique can be applied equally to both NBTI and PBTI. Experimental results using Cadence Relxpert on critical paths extracted from industry designs show that with a negligible power, area overhead, a significant improvement (50%) in the total degradation of critical path performance with respect to end-of-life models is achievable.