Delay test vector generation has emerged as an increasingly critical problem in high performance VLSI designs. Existing techniques achieve estimated timing critical paths by STA or SSTA, for which a subsequent traditional ATPG method finds corresponding test vectors. In this paper, we propose a new delay test vector generation method, which achieves estimated timing critical paths by more accurate vector-based statistical timing analysis, achieves input vectors by back-tracing, and verifies the estimated timing critical paths under the input vectors by logic simulation. We observe that as a MAX operation leads to the maximum signal arrival time at the output of a gate, multiple simultaneous signal propagation paths lead to the worst case performance of a combinational logic block in the presence of performance variation. We propose delay test generation for a signal propagation network instead of a signal propagation path. Our experimental results based on 7 ISCAS'89 benchmark circuits show that while the state-of-the-art SSTA-TQM-BnB technique achieves an average of 20.5%, 18.5%, and 18.5% delay fault coverage, our SPSTA-Network technique achieves an average of 94.2%, 92.7%, and 96.0% delay fault coverage for a test size of 20, 50, and 100, respectively.