Performance and Cache Access Time of SRAM-eDRAM Hybrid Caches Considering Wire Delay

Young-Ho Gong,  Hyung Beom Jang,  Sung Woo Chung
Department of Computer and Radio Communication Engineering, Korea University


Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip caches becomes larger. The increased cache size causes the leakage power and area of the on-chip caches to increase. Recently, to reduce the leakage power and area of the SRAM based cache, the SRAM-eDRAM hybrid cache was proposed. For SRAM-eDRAM hybrid caches, however, there has not been any study to analyze the effects of the reduced area on wire delay, cache access time, and perfor-mance. By replacing half (or three fourth) of SRAM cells by small eDRAM cells for the SRAM-eDRAM hybrid caches, wire length is shortened, which eventually results in the re-duction of wire delay and cache access time. In this paper, we evaluate the SRAM-eDRAM hybrid caches in terms of the energy, area, wire delay, access time, and performance. We show that the SRAM-eDRAM hybrid cache reduces the energy consumption, area, wire delay, and SRAM array access time by up to 53.9%, 49.9%, 50.4%, and 38.7%, respectively, compared to the SRAM based cache.