Hetero2 3D Integration: A Scheme for Optimizing Efficiency/Cost of Chip Multiprocessors

Shivam Priyadarshi1,  Niket Choudhary1,  Brandon Dwiel1,  Ankita Upreti1,  Eric Rotenberg2,  Rhett Davis3,  Paul Franzon2
1Graduate Student, North Carolina State University, Raleigh, 2Professor, North Carolina State University, Raleigh, 3Associate Professor, North Carolina State University, Raleigh


Timing the transition of a processor design to a new technology poses a provocative tradeoff. On the one hand, transitioning as early as possible offers a significant competitive advantage, by bringing improved designs to market early. On the other hand, an aggressive strategy may prove to be unprofitable, due to the low manufacturing yield of a technology that has not had time to mature. We propose exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP). First, 3D integration facilitates a technology alloy. The CMP is split across two dice, one fabricated in the old technology and the other in the new technology. The alloy derives benefit from the new technology while limiting cost exposure. Second, to compensate for lower efficiency of old-technology cores, we exploit application and microarchitectural heterogeneity: applications which gain less from technology scaling are scheduled on old-technology cores, moreover, these cores are retuned to optimize this class of application. For a defect density ratio of 200 between 45nm and 65nm, Hetero2 3D gives 3.6x and 1.5x higher efficiency/cost compared to 2D and 3D homogeneous implementations, respectively, with only 6.5% degradation in efficiency. We also performed the sensitivity analysis by sweeping the defect density ratio and our results highlight the defect density break-even point, where homogeneous 2D and 3D designs in 45nm achieve the same efficiency/cost as Hetero2 3D, marking a significant point in the maturing of the technology.