In this paper, we demonstrate that signal lines in SRAM arrays are prone to electromigration (EM). Our analysis shows that the read operation can cause unidirectional current flow in bit-lines. Thus the length of bit-lines should be bounded not only by performance requirements, but also by the Blech length constraint to avoid EM. We propose a method of determining the bit-line width under layout constraints to maximize the number of cells attached to a bit-line, while ensuing the reliability of the bit-line and maintaining SRAM performance. We also study the effects of SRAM parameter variations on the EM-safe bit-line length. Simulation results show that the EM-safe bit-line length decreases as technology scales, temperature or frequency rise, and parameter variations increase.