Suspicious Timing Error Prediction with In-Cycle Clock Gating

Youhua Shi,  Hiroaki Igarashi,  Nozomu Togawa,  Masao Yanagisawa
Waseda Univ.


Conventionally, circuits are designed to add pessimistic timing margin to resolve delay variation problems, which guarantees “always correct” operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error detection/recovery method for per-formance and energy efficiency improvement in pipeline designs. Experimental results show that when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement; or 2) be overclocked by up to 1.88X with in-situ timing error detection/recovery ability.