High-speed DFG-level SEU Vulnerability Analysis for Applying Selective TMR to Resource-Constrained CGRA

Takashi Imagawa,  Hiroshi Tsutsui,  Hiroyuki Ochi,  Takashi Sato
Kyoto University


selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of an application circuit to a coarse-grained reconfigurable architecture (CGRA). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the features and parameters of each node in the DFG which characterize impact of the SEU in the node to the output data.

This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. The proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours.