Framework for Analog Test Coverage

Debesh Bhatta1,  Ishita Mukhopadhyay2,  Suriyaprakash Natarajan3,  Prashant Goteti3,  Bin Xue3
1Georgia Institute of Technology, 2Cornell University, 3Intel Corporation


Measurement of the quality of tests run during high volume manufacturing of microprocessors is important to ensure desired outgoing product quality. For digital logic on die, such measurement is performed using techniques such as fast event-driven fault simulation using mature fault models such as stuck-at and transition faults. For analog modules on die, such test quality measurement is not performed in practice due to lack of (a) mature fault models to describe analog failures, and (b) automated, efficient and accurate fault simulation methods. This work is a first step towards our objective of establishing a practical methodology to measure analog test quality. We show promising results of a semi-automated fault simulation approach on analog modules of a high speed serial IO receiver that compares (a) two manufacturing tests in terms of their defect detection capability as measured by their fault coverages for gross and parametric faults, and, (b) the accuracy and performance of using models versus schematics for fault effect propagation.