A Cost-effective 45nm 6T-SRAM Reducing 50mV Vmin and 53% Standby Leakage with multi-Vt Asymmetric Halo MOS and Write Assist Circuitry

Koji Nii1,  Makoto Yabuuchi1,  Hidehiro Fujiwara1,  Yasumasa Tsukamoto1,  Yuichiro Ishii1,  Tetsuya Matsumura1,  Yoshio Matsuda2
1Renesas Electronics Corporation, 2Kanazawa University


We propose an enhanced high-density 6T-SRAM bitcell with mutli-Vt asymmetric halo implant dose MOSFET (AH-MOS) by introducing additional masks. Modified mask structures contributes to reduce the number of halo implant dose masks and achieve dense 0.37 um^2 6T-SRAM bitcell without any area overhead, shrinking to a half size of our previous work. 4-Mbit SRAM test chips are fabricated using 45-nm bulk CMOS technology. Combining with write assist circuitry, the Vmin is reduced by 50 mV and standby leakage by 53%.