Temperature Aware Thread Migration in 3D Architecture with Stacked DRAM

Dali Zhao1,  Houman Homayoun2,  Alex V. Veidenbaum1
1University of California, Irvine, 2George Mason University


A 3D architecture with DRAM memory stacked on a multi-core processor has many benefits for the embedded system. Compared with conventional 2D design, it reduces memory access latency, increases memory bandwidth and reduces energy consumption. However it poses a thermal challenge as the heat generated by the processor cannot dissipate efficiently through the DRAM memory layer. Due to the fact that DRAM is very sensitive to high temperature as well as temperature variance, stacking in 3D causes more failures to occur because DRAM thermal variance is higher than than in the 2D case. To address this thermal challenge we propose to reduce temperature variance and peak temperature of a 3D multi-core processor and stacked DRAM by thermally aware thread migration among processor cores. This method has very limited impact on processor performance. Using migration-based policy we reduce peak steady-state temperature in the processor by up to 8.3 degrees Celsius, with the average of 4.7 degrees.