Canonical Ordering of Instances to Immunize the FPGA Place and Route Flow from ECO-Induced Variance

Avijit Dutta,  Neil Tuttle,  Krishnan Anandh
Cypress Semiconductor Corporation


Engineering change order (ECO)s for FPGA-based designs often require design changes late in the design process to correct functional, timing, technological problems. After an ECO process a small portion of the circuit netlist is changed. To take advantage of the enormous resources and time already spent on place and route flow, it is desirable to maintain similar post-routing delay characteristics to the pre-ECO stage to avoid further expensive design iterations. Most FPGA tools use the variance to their advantage to explore the solution space in the design optimization phase. The embedded systems companies cannot afford multiple pass compile times especially in ECO situations. The variance reduction technique proposed in this paper is applicable only in the ECO situations and not during design optimization phase where variance plays an advantageous role. Predictability is not just unique to ECO, but success of an ECO is highly dependent on predictability and that’s where the proposed approach plays a crucial role. We propose a fast canonical ordering technique that either guarantees either a unique instance order or minimized the perturbation to the instance order as seen by the P&R flow and thereby reduces or eliminates post-routing delay variance.