A Low Power Deflection Routing Method for Bufferless NoC

Chung-Kai Hsu1,  Kun-Lin Tsai2,  Jing-Fu Jheng1,  Shanq-Jang Ruan1,  Chung-An Shen1
1National Taiwan University of Science and Technology, 2Tunghai University


Network-on-chip has been proposed for high performance on-chip communication. A major component of the network-on-chip architecture is the router, which affects the data transmission latency, chip area and power consumption. Inside the router, the buffers consume significant power and area. Bufferless NoC, which discards the buffers in the routers, is proposed for solving the power and area problem. In this paper, a low power deflection routing method is proposed for the bufferless on-chip network dealing with the routing problem and achieving the low power goal. The proposed method uses routing matrix for constructing the possible routing path, and then selects the best route for each data packet. Only few calculations are used in this method for achieving the low power goal. The experimental result shows that the power consumption is 56% lower and the chip area is 52% smaller than the previous research.