Optimizing energy consumption for electronic systems has been an important design consideration. Multi-power domain design is widely used for low power and high performance applications. Data transfer between power domains needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which leads to large area and performance overhead. In this paper, we proposed a CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. Our design separates power rails in each tier, substantially reduced physical design complexity and area penalty. The design is implemented in a 45nm low power technology. It shows 20%-35% smaller clock to Q and ~30% energy saving comparing with existing LCFF designs. The proposed design also shows better robustness with +/-10% voltage variation.