System-Level Modelling of Dynamic Reconfigurable Designs using Functional Programming Abstractions

Bahram Najafi Uchevler1,  Kjetil Svarstad1,  Jan Kuper2,  Christiaan Baaij2
1Department of Electronics and Telecommunication, NTNU, Norway, 2Department of Computer Science, University of Twente


With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.