Enabling Sizing for Enhancing the Static Noise Margins

Valeriu Beiu1,  Azam Beg1,  Walid Ibrahim1,  Fekri Kharbash1,  Massimo Alioto2
1UAEU, 2U Michigan Ann Arbor


This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes. The method relies on upsizing the length (L) of all transistors and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). We use the most well-known CMOS gates (INV, NAND-2, NOR-2) for presenting the novel sizing method, as well as for verifying the concept and evaluating its performances. The results show that sizing has not yet exhausted its potential, allowing to go beyond the well established delay-power tradeoff, as sizing can increase SNMs by: (i) adjusting the threshold voltages (VTH); and (ii) balancing the VTCs. Simulations show that this sizing method enables more reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which could operate correctly at very low supply voltages, hence, also enabling circuits for ultra-low voltage/power.