Large on-chip caches account for a considerable fraction of the total energy consumption in modern and future microprocessors. Emerging Spin-Transfer Torque RAM (STT-RAM) has been regarded as a promising candidate to replace large on-chip SRAM caches in virtue of its nature of zero leakage. However, large write energy requirement of STT-RAM, resulting in a huge amount of dynamic energy consumption, precludes it from application to on-chip cache design. To reduce the write energy of the STT-RAM cache, we propose an architectural technique, which exploits the fact that many applications manipulate a large number of zero data. The proposed design appends an all-zero-data flags at the byte or the word granularity in cache tag arrays and set these all-zero-data flags if the corresponding write byte or word is zero data, whose all data bits are zero. Our evaluation results show that we can reduce a write dynamic energy over 60%; in a total energy considering both of read and write operation, we can save 23.61% and 31.57% at the byte and word granularities, respectively. Performance simulation results also show that the proposed cache improves the processor performance by 5.45% on average.