Statistical Methodology for Modeling Non-IID Memory Fails Events

Sabine Francis1,  Rouwaida Kanj1,  Rajiv Joshi2,  Ayman Kayssi1,  Ali Chehab1
1American University of Beirut, 2IBM TJ Watson Labs


We propose a comprehensive and computationally efficient methodology for the estimation of correlated memory fail probabilities. The methodology allows, for the first time, to accurately predict the number of failing memory parts in the presence of correlation between the memory fails due to shared peripheral logic. It relies on importance sampling to model the fail region and emulate different memory architectures. Unlike traditional yield analysis methodologies that assume independent and identically distributed fail events, we record a high overdispersion rate, variance to mean ratio, due to the correlations. This in turn leads to an increase in the number of memory bit fails compared to IID events and is itself a strong function of the memory/peripheral logic grouping. Under extreme operating conditions, our experiments demonstrate overdispersion ratios larger than 10, and more than 23% increase in the number of fails at the 90th percentile level of the array samples/population. However, from a redundancy perspective, the correlations result in reduced column redundancy quota requirements with demonstrated cases with more than 20% reduction in the required quota compared to the IID assumption.