Impact of FinFET Technology for Power Gating in Nano-Scale Design

Keunwoo Kim1,  Rouwaida Kanj2,  Rajiv Joshi3
1Samsung, 2American University of Beirut, 3IBM TJ Watson


This paper presents the first detailed analysis of power gating structures in sub-nano scale FinFET circuits. FinFETs are compared with their bulk CMOS counterpart devices to gain design perspective for purposes of power-gating applications. Circuit performance, power, and leakage are analyzed. TCAD device/circuit mixed-mode simulations for a FinFETbased ring oscillator with footer structure are employed to study the implications of the physical properties of FinFET power-gating devices. A critical evaluation of the virtual ground bounce for the proposed power-gating scheme is presented providing an insight into low-power applications in FinFET circuits. For low voltage operation the ground bounce is found comparable to that of bulk-Si while maintaining 40% reduction in delay. FinFET specific design metrics are analyzed as function of power-gating device size in the power-gating structure indicating larger leakage current sensitivity compared to bulk and room for leakage envelope optimization.