Concurrency-Oriented SoC Re-Certification by Reusing Block-Level Test Vectors

Hsuan-Ming Chou,  Hong-Chang Wu,  Yi-Chiao Chen,  Shih-Chieh Chang
National Tsing Hua University


The complexity of verifying a System on Chip (SoC) increases dramatically due to the integration of heterogeneous components and complicated interactions among components. Despite the functional features and corner cases of a component could be exercised thoroughly during block-level verification, it is important to re-certify the component after integrating into an SoC. In this paper, we propose an Interaction Dependency Graph (IDG) to reuse block-level test vectors for component re-certification. We discuss and resolve the problems of reusing block-level test vectors. Moreover, the maximum number of concurrent interactions are inserted into the IDG to expose critical bugs in an SoC. We demonstrate our approach on Nios II SoC and show that we can efficiently re-certify SoC components. We also discuss an industrial experience of uncovering a concurrency-related bug.