Building Energy-Efficient Multi-Level Cell STT-MRAM Based Cache Through Dynamic Data-Resistance Encoding

Ping Chi1,  Cong Xu1,  Xiaochun Zhu2,  Yuan Xie1
1Pennsylvania State University, 2Qualcomm Incorporated


In this paper, we focus on mitigating the energy consumption during multi-level cell (MLC) STT-MRAM write operations. Based on the strong dependency of write energy on data values, a dynamic data-resistance encoding technique is proposed to map the most frequently appearing data values to the most energy-efficient resistance states at runtime. Our experimental results show that, compared with the existing static data mapping scheme, our technique reduces write energy by 12.1% on average and up to 25.4% for a typical MLC STT-MRAM cache.