Silicon Physical Unclonable Functions (PUF) have shown great promise for implementing chip IDs in a secure and inexpensive way. Bi-stable PUFs are particularly attractive as they inherently generate binary data. One of the major problems with bi-stable PUFs is their reliability to temperature variations. In this work, we improve the reliability of bi-stable PUFs by exploiting the differences between pMOS and nMOS in the threshold voltage (Vth) variation and in the dependence of Vth on temperature. Based on the 90nm simulations, the proposed circuit-level techniques show about a 70% reduction in the number of unreliable bits. We show that significant area savings can be achieved with improved reliability as the cost of error correction codes (ECC) implementation can be greatly minimized. We further show the applicability of the proposed technique in 130nm and 65nm.