Heterogeneity Exploration for Peak Temperature Reduction on Multi-Core Platforms

Tianyi Wang1,  Ming Fan1,  Gang Quan1,  Shangping Ren2
1Florida International University, 2Illinois Institute of Technology


As IC technology continues to evolve and more and more transistors are integrated into a single chip, high chip temperature due to high power density not only increases packaging/cooling cost but also severely degrades reliability and the performance of computing systems. In the meantime, as transistor feature size continues to shrink, it becomes difficult to precisely control the manufacturing process. The manufacturing variations can cause significant differences from core to core and chip to chip. We believe that the heterogeneity due to manufacturing variations, if handled properly, can in fact improve the design objectives of real-time applications. In this paper, we study the problem on how to reduce the peak temperature of a real-time application by judiciously mirroring the physical architecture of an individual device to the logical architecture based on which the application was designed under manufacturing variations. We develop three computationally efficient algorithms that can be used when deploying an application to an individual device. Our simulation study has clearly shown that, by taking advantage of the uniqueness of each physical chip, the proposed approach are light-weighted and can significantly reduce the peak temperature.