Increase in power density and interconnect resistance along with decrease in supply voltage due to scaling has resulted in large IR drop. IR drop analysis and maximization is an important element of power supply network design and manufacturing testing. In this paper, we examine IR-drop analysis problem for combinational circuits. The solution to the general problem of maximizing IR drop of a power supply network can be reformulated as a pattern generation problem to maximize IR drop at a specific point. The main contributions of this paper are (i) formulation of objective function for pattern generation using the spatial location and strengths of the gates and (ii) expressing the Boolean relationships between gates to use in an Integer Linear Programming solver for solving the pattern generation problem. We further show that by exploiting the conic structure of combinational circuits and the proposed formulation, the technique is easily applied to larger circuits. The proposed technique was applied to ISCAS-85 benchmark circuits and validated in simulation. Results show that with targeted pattern generation and deterministic approach, we achieve ~25 % greater IR drop aggravation over random patterns on an average, while average run-time improves by four orders of magnitude.