In this work, we propose a fast tool to compute the variation (σ/µ) of delay for any logic path in a synthesized design for any given process corner. The proposed method does not require deep understanding of device physics, prior knowledge of the design, or extensive Monte Carlo simulation, and it provides good accuracy with less than 11% error. We also demonstrate the importance of using variation estimation methods to identify critical paths in sub-threshold designs, as the logic path with longest nominal delay may not have the greatest stochastic delay (µ+xσ).