Power delivery network (PDN) design is one of the most critical challenges in 3D IC design. In existing studies, the IR-drop constraints were considered identical on each layer of the 3D chip and the number of TSVs was always increased to mitigate the IR-drop and power noise. The increase of TSVs may introduce more keep-out zones, decrease the core utilization of the chip, and lead to high cost. In this paper, we propose a region-aware TSV planning algorithm which can distribute TSV resources non-evenly over different areas according to their IR-drop constraints separately. This method can use fewer power TSVs to meet the power integrity constraint of the whole chip while guaranteeing the functionality. Furthermore, to ensure the practicability, we also take the whitespace into account. Experimental results show that the region-aware TSV planning algorithm can save on average 42% of the power TSV resources compared with the evenly TSV planning algorithm.