This paper presents a four-level pulse amplitude modulation (4-PAM) memory I/O interface for 3D stacked DRAMs. 3D integration technology is a promising solution for higher bandwidth and less power consumption due to the shortened link distance. The proposed transceiver is designed for 3D interconnects. The proposed transmitter employs a current mode output driver which sends data through TSVs. The receiver side uses differential amplifiers to decode three voltage levels by comparing the PAM signal with three reference voltages. The proposed scheme is simulated in 40 nm CMOS technology at 1.0 V. We use a highly accurate 3D electromagnetic (EM) simulator such as HFSS for 3D TSV channels simulations. The proposed architecture reduces the power consumption compared with prior works. It also increases the data bandwidth to 6.4 Gb/s/pin. Energy efficiency of proposed 3D mobile PAM I/O memory interface is 1.7 pJ/bit/pin.