Electromigration (EM) greatly affects the long term reliability of VLSI chips. Not only power/ground (P/G) lines, but also bit-lines of SRAM arrays may be damaged by EM. In this work, we demonstrate that the EM reliability of an SRAM array can be dramatically worsened by process variation due to a significant increase of sub-threshold leakage current on the bit-line. We statistically model the effects of process variation and offer a procedure for preventing EM failure by modifying the width of bit-lines and P/G lines. Taking into account the effect of bit-line width modification on cell stability and performance, we propose a trade-off between functional and EM failures and indicate an optimal bit line width that maximizes the yield of SRAM arrays.