The work highlights the potential benefits of operating Junctionless (JL) Double Gate (DG) MOSFETs in the volume accumulation mode. An optimized 20 nm JL MOSFET in volume accumulation achieves impressive intrinsic delay value of 9 ps and on-off current ratio of ~1e6 at a gate and drain bias of 0.4 V (subthreshold region). These values are significantly better than traditional JL MOSFETs designed with higher doping concentration (> 1e19 /cm3). The maximum sensitivity of threshold voltage is limited to 3.5% for a 10% change in device parameters. The constraints for gate workfunction are less stringent in volume accumulated JL MOSFETs. A JL 6T-SRAM cell achieves an impressive read and hold noise margins of 156 mV and 364 mV along with a write-ability current of 20 micro A at a supply voltage of 0.8 V. The paper presents new viewpoints for the design and optimization of junctionless transistors and circuits for low power logic technology applications.