Technology/Circuit Co-optimization and Benchmarking for Graphene Interconnects at Sub-10nm Technology Node

Chenyun Pan1,  Praveen Raghavan2,  Francky Catthoor2,  Zsolt Tokei2,  Azad Naeemi1
1Georgia Institute of Technology, 2IMEC


In this paper, graphene interconnects are analyzed based on realistic circuits in terms of multiple material properties, such as the mean free path, the contact resistance, and the edge roughness. The benchmark against conventional copper wires shows that the advantage of graphene usage occurs only under certain circumstances. The device-level parameters, including the supply and threshold voltages, and the circuit-level parameters, including the wire length and width, have large impacts on both the delay and energy-delay roduct (EDP) comparisons. Two representative circuits, a 32-bit adder and an SRAM, are investigated. Up to 40% and 70% of the improvement in delay and EDP are observed for a 32-bit adder. For the SRAM application, contact resistance is a crucial factor in dictating the performance of graphene interconnects.