Cells Reconfiguration around Defects in CMOS/Nanofabric Circuits using Simulated Evolution Heuristic

Abdalrahman M. Arafeh1 and Sadiq M. Sait2
1University of British Columbia, 2King Fahd University of Petroleum & Minerals


CMOS/nanofabric hybrid circuits combine the flexibility and high fabrication yield advantages of CMOS technology with ultra fast nanometer-scale devices. CMOL is a novel architecture which consists of a nanofabric overlay on top of a CMOS stack. CMOL can be configured to implement NOR-based logic circuits by programming nanodevices placed between the nanofabric's overlapping nanowires. Defect rate in nanofabric-based circuits is expected to be higher than that of conventional CMOS technology. Misassembly of nanodevices will lead to non-programmable crosspoints, while broken nanowires will result in unreachable circuit's components.

In this work, we propose a heuristic-based nanofabric reconfiguration around defects in CMOL circuits. Simulated Evolution (SimE) is formulated to find circuits configurations that adhere to nanowires connectivity constraint and rely on non defective components. Circuits of various sizes from ISCAS'89 benchmarks were used to evaluate our proposed design. Results show that SimE yield successful reconfigurations in acceptable computation time when up to 50% of nanodevices are stuck-at-open and 70% of nanowires are broken.