User Power-Delay Budget Driven PSO Based Design Space Exploration of Optimal k-cycle Transient Fault Secured Datapath during High Level Synthesis

Anirban Sengupta and Saumya Bhadauria
Indian Institute of Technology, Indore


Fault security indicates ability to provide error detection or fetching the correct output. Generation (design space exploration (DSE)) of an optimal fault secured datapath structure based on user power-delay budget during high level synthesis (HLS) in the context k-cycle transient faults is considered an intractable problem. This is due to the fact that for every type of candidate design solution produced during exploration, a feasible k-cycle fault secured datapath may not exist satisfying the conflicting user constraints/budget. Secondly, insertion of inapt cut to optimize delay overhead associated with fault security in most cases may not yield optimal solutions in the context of user constraints/budgets. The solutions to the above problems have not been addressed in the literature so far. The paper solves the problem by presenting: (a) a novel algorithm for fault secured particle swarm optimization driven DSE (b) novel technique for handling k-cycle transient faults (c) novel schemes for selecting appropriate edges for inserting cuts in the scheduled Control Data Flow Graph (CDFG) minimizing delay overhead associated with fault security. The proposed approach yielded optimal results which minimizes hybrid cost as well as satisfies user constraints. Further, results of comparison with recent approaches indicated significant reduction of final cost.