6-T SRAM Performance Assessment with Stacked Silicon Nanowire MOSFETs

Ya-Chi Huang1,  Meng-Hsueh Chiang2,  Wei-Chou Hsu2,  Shiou-Ying Cheng1
1National Ilan University, 2National Cheng Kung University


This paper assesses the 6-T SRAM performance and provides the design methodology with stacked gate-all-around silicon nanowire MOSFETs. To achieve high density design while preserving performance, different numbers of stacked nanowire MOSFETs are investigated via three-dimensional TCAD simulation. Due to the tradeoff between read stability and writeability, changing the relative strengths of the transistors is needed but it can not be done straightforwardly as the widths of transistors are now quantized. Furthermore, when 3D stacking technique is used, another design issue with various stacked transistors has to be accounted for. This work provides an optimal design methodology for feasible manufacturability and good performance while using high density stacking technique. Our results suggest that for the same stacked layers, though high staking number favors writeability, it is limited to three layers due to serial source/drain resistance.