A 4-14 Gbps Inductor-Less Adaptive Linear Equalizer in 65nm CMOS Technology

Govardhana Rao Talluri,  Rakesh K K,  Maryam Shojaei Baghini
IIT Bombay


This paper presents an inductor-less adaptive linear equalizer using a proposed tunable hybrid active filter comprising both low-pass and high-pass filters within a power detector. This technique leads to tunability of the adaptive linear equalizer over a wide range of throughput from 4 Gbps to 14 Gbps. The entire equalizer circuit is designed, optimized and post layout extracted in 65 nm CMOS technology. Post layout simulations of the equalizer show the throughput up to 14 Gbps for sever conditions of channel losses up to 12 dB at 7 GHz, package reflections and industry compatible worst case jitter of 33% at the transmitter. The adaptive equalizer has been loaded with single-ended 150 fF capacitor and exhibits worst case power density of 1.8 mW/Gbps.