A methodology and analytic expressions are proposed to appropriately allocate the available physical area to through silicon vias (TSVs) and sleep transistors in three-dimensional (3D) ICs with power gating. Power supply noise is minimized by the proposed resource allocation methodology while satisfying the required constraints on leakage current and turn-on time. A comprehensive simulation setup of a three plane 3D IC is developed to evaluate the accuracy and efficacy of the proposed methodology. The proposed expressions exhibit an error of 4% as compared to simulation results. The simulation results also demonstrate that the power supply noise is reduced by more than 46% while satisfying both turn-on time and leakage current.