Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC

Seungwon Kim,  Seokhyeong Kang,  Ki Jin Han,  Youngmin Kim
Ulsan National Institute of Science and Technology, Republic of Korea


Among power dissipation components, leakage power has become more dominant with each successive technology node. The power gating technique has been widely used to reduce the standby leakage energy. In this work, we investigate the power gating strategy of TSV-based 3D IC stacking structures. The power gating control is becoming more complicated as more dies are stacking. We combine the on-chip PDN and TSV in multi-layer 3D IC for power gating analysis in the static and dynamic voltage drop and in-rush current. Then we propose a novel power gating strategy which optimizes the in-rush cur- rent profile subject to voltage drop constraints. Our power gating strat- egy provides minimal wake-up latency such that voltage noise safety margins are not violated. In addition, layer dependency of 3D IC on the power gating in terms of the wake-up time reduction is analyzed. We achieve average 28% wake-up time reduction for all cases with our adaptive power gating method which exploits location (or layer) infor- mation of the aggressors in 3D IC.