Analog/Mixed-Signal (AMS) circuits present significant challenges to designers with the increase of design complexity and aggressive technology scaling. Design optimization techniques that account for process variation while presenting an accurate and fast design flow which can perform design optimization in reasonable time are still lacking. As a trade-off of the accuracy and speed, this paper presents a process-variation aware design flow for ultra-fast variability-aware optimization of nano-CMOS based physical design of analog circuits. It combines Kriging bootstrapped Neural Network (KBNN) metamodels with a Particle Swarm Optimization (PSO) algorithm in the design optimization flow. The KBNN provides a trade-off between analog-quality accuracy and scalability and can be effectively used for large and complex AMS circuits while capturing correlations in process variations. The effectiveness of the design flow is demonstrated using a 180nm CMOS based PLL as a case study with 21 design parameters. The KBNN metamodel is 24$\times$ faster than NN metamodeling.