Electrical Characteristic and Power Consumption Fluctuations of Trapezoidal Bulk FinFET Devices and Circuits Induced by Random Line Edge Roughness

Chieh-Yang Chen,  Wen-Tsung Huang,  Yiming Li
National Chiao Tung University


In this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. The fixed top-fin width of all trapezoidal bulk FinFET devices with different fin angle are considered in this study. By adopting a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFETs. For each type of LER, the threshold voltage (Vth) fluctuation is independent of fin angles. The resist-LER is most influential on characteristics’ fluctuation. For the same type of LER, spacer-LER has at least 85 % improvement on Vth compared with resist-LER. Moreover, the fin width variation is the main reason instead of different extent of roughness scattering by comparing resist-LER with spacer-LER. As for the digital circuit characteristic, the rectangle-shape bulk FinFET has larger timing fluctuation.