Early design analysis is essential for better design definition and efficient balancing of design effort and risk. In this paper, we introduce the concept of virtual logic netlist (VLN), a potentially incomplete yet representative hierarchical and logical netlist graph of the design. VLN enables early and rapid register transfer level (RTL) analysis using accurate backend tool engines without the need for time-intensive synthesis techniques. We discuss the creation of a VLN, and its application to enable RTL clock gating analysis. Experimental evaluation performed on the IBM POWER8 microprocessor chip showed an error of less than 2%, and a TAT improvement of atleast 250x, when compared to full netlist based analysis.