An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation

Jun Shiomi,  Tohru Ishihara,  Hidetoshi Onodera
Kyoto University


On-chip memory is one of the most energy consuming components in processors. Aggressive voltage scaling to the sub-/near-threshold region is thus applied even to the memory used for ultra-low power applications. In this paper, an energy efficient cell-based memory structure which is stably working with a near-threshold operating voltage is proposed. The circuit simulation using a commercial 28-nm technology shows that the energy consumption for the readout operation in our memory proposed here is up to 69% less than the energy dissipated in an existing cell-based memory or a conventional SRAM circuit. The simulation using a foundry provided Monte Carlo package also shows that the 3σ worst case read-access time of our cell-based memory is comparable to that of the SRAM circuit.