Optimal Choice of FinFET Devices for Energy Minimization in Deeply Scaled Technologies

Mohammad Saeed Abrishami,  Alireza Shafaei,  Yanzhi Wang,  Massoud Pedram
University of Southern California


FinFET devices are considered to be device substitutes for bulk CMOS at the 22nm technology node and beyond due to the reduced short-channel effects, improved ON/OFF current ratio, and improved voltage scalability. This paper investigates the problem of optimal selection of deeply-scaled FinFET technology to achieve minimum energy consumption for different applications, e.g., sensor applications, smartphones, embedded micro-processors, or server microprocessors, which differ from each other in the required performance and duty ratio. For each application space, different FinFET technologies (with different Vth and gate length biases) are compared for minimum energy consumption for both logic circuits and cache memories. A device-circuit-architecture cross-layer framework has been developed to facilitate this technology selection. This optimal technology selection procedure demonstrates up to 11X energy saving compared to poorly selected technologies.