Incremental ATPG Methods for Multiple Faults under Multiple Fault Models

Masahiro Fujita1,  Alan Mishchenko2,  Naoki Taguchi1,  Kentaro Iwata1
1University of Tokyo, 2University of California, Berkeley


We propose a general framework for incremental automatic test pattern generation of combinational circuits targeting multiple faults under multiple fault models. Not only standard fault models, such as stuck-at faults, but also any functional fault models can be targeted, once the fault model is given in terms of the resulting logic functions under the faults. Given sufficient time, the proposed methods can automatically generate complete sets of test patterns for multiple standard and/or custom faults. Although there are exponentially many combinations of multiple faults, the proposed SAT based formulation can generate test patterns for all of them incrementally. As a consequence, as long as the required numbers of test patterns are not so many, which has been the case for all of our experimental results, we can finish generating complete sets of test patterns. We have implemented the proposed methods, and through experiments we show that complete sets of test patterns targeting multiple faults under various fault models for circuits having up to tens of thousand of gates can be automatically generated. As any functional faults can be dealt with the proposed methods, they can also be applied to circuit transformation based logic synthesis.