A Digitally-Controlled Power-Aware Low-Dropout Regulator to Reduce Standby Current Drain in Ultra-Low-Power MCU

Kaushik Mazumdar1,  Steven Bartling2,  Sudhanshu Khanna2,  Mircea Stan1
1University of Virginia, 2Texas Instruments


In this paper, we describe a fully-integrated digitally-controlled low-dropout regulator (LDO) with dual-loop architecture, providing core voltage to an ultra-low-power MCU. The fine-grained loop dynamically modulates the active-mode LDO drive-strength using the MCU power-modes information for a maximum load current of 6mA, thereby improving the active-mode current efficiency. The coarse-grained loop, enabled only when the MCU enters the standby-mode to regulate the output voltage, ensures the lowest quiescent current consumption of 500nA among state-of-art LDOs, preventing standby current drain. A thermometric binary-weighted power switch matrix improves the transient response figure-of-merit (FOM) by switching between the different power modes. A charge-pump based voltage monitoring circuit is added to allow wider range of input voltage with reduced ripple. Fast digitally-controlled transient response of the LDO has allowed us to replace the external big capacitor with high-density on-chip ferroelectric capacitor, thereby reducing the LDO sleep-to-active recovery time/energy and allowing full system-on-chip integration. The digitally-controlled LDO, with a wide input voltage range of 1.75-3.3V and nominal output of 1.2V is implemented in a 0.13┬Ám CMOS technology with an active area of 0.034mm2, achieving a FOM of 4.44ps with standby-mode current efficiency of more-than 90% for all practical purposes.