Power dissipation is a major concern in sub-nanometer IC designs with technology scaling pushing towards higher clock frequencies. Techniques such as dynamic voltage (and frequency) scaling (DVS) to minimize power while providing good throughput have become commonplace. This paper presents a fully pipelined 256-bit key advanced encryption system (AES) design implemented with power-saving pulse-clocked latches as pipeline flip-flops that supports pipeline collapse. The design is fabricated on a foundry 90-nm low standby power process. Measured results show the design is capable of 64 Gb/s encryption. A 7.6% decrease in the energy per operation beyond the frequency scaling based power reduction using pipeline stage combining is obtained.