Layout-aware Analog Synthesis Environment with Yield Consideration

Hsin-Ju Chang,  Yen-Lung Chen,  Conan Yeh,  Chien-Nan Liu
National Central University


For an automatic analog synthesis tool, the generated performance and yield is unexpected if the non-ideal effects are not considered, which often result in time-consuming sizing-layout iterations. In this paper, an integrated analog synthesis tool is presented to consider the process variation, layout effects, and final layout generation simultaneously, with a user-friendly GUI to help users complete the design flow efficiently. Since the possible performance degradation has been considered, no preserved design margins and re-design cycles are required in the proposed tool, which significantly reduces the design overhead. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance and design yield with less hardware cost.